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Implementation Hints
The following implementation ( Figure 7-4 on page 62 ) implements an extra buffer level in the backend.
The core writes the received data to the small 32×16 memory block. At the end of the transfer, the
backend RX state machine captures the TSW value, then bursts the complete receive packet into main
memory. This system enables the complete message to be copied to main memory once completely
validated. It will stay intact in main memory until the complete following message of at least 40 μs is
received.
RX
Buffer
32×16
Read Write
BUSAINEN
BUSAINP
BUSAINN
RX
State
Machine
TX
Memory
2k×16
Write Read
BUSAOUTIN
BUSAOUTP
BUSAOUTN
BUSBINEN
BUSBINP
BUSBIN
BUSBOUTIN
BUSBOUTP
BUSBOUTN
Core1553BRT
Figure 7-4 ? Buffer Management Circuit
Buffer management techniques are system-dependent. They depend on the bus traffic scheduling by the
bus controllers. The Core1553BRT implementation is intended to provide a flexible interface that can be
adapted to the system requirements.
Bus Transceivers
Core1553BRT does not include the transceiver that is required to drive the 1553B bus. Core1553BRT is
designed to interface directly to MIL-STD-1553 transceivers. There are several suppliers of MIL-STD-
1553 transceivers, such as DDC (BU-63147) and Aeroflex (ACT4402).
When using Fusion, IGLOO/e, ProASIC3/E, ProASIC PLUS , or Axcelerator FPGAs, level translators are
required to connect the 5 V outputs of the 1553B transceivers to the 3.3 V inputs of the FPGA.
In addition to the transceiver, a pulse transformer is required for interfacing to the 1553B bus. Figure 7-5
transceivers and then to the bus via pulse transformers.
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